mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 PS51277-A integrated power functions dc input, three-phase ac output inverter 600v, 15arms (input current) application ac100~200v active-converter for pfc (power factor correction), of air-conditioner and so on. fig. 1 package outlines mitsubishi semiconductor PS51277-A transfer-mold type insulated type integrated drive, protection and system control functions igbt s driver circuit control supply under-voltage (uv) protection input interface : 5~15v line cmos/ttl compatible, schmitt trigger receiver circuit dimensions in mm detail a detail b type name , lot no. a b 21 terminal 9. 10. 11 terminal 2- 4.5 0 .2 heat sink (71) 16 1 8 0.5 31 0.5 28 0.5 8 0.8 0.6 2 1.8 1.4 13.4 0.5 21.4 0.5 11.5 0.5 79 0.5 27 2.8(=75.6) 2.8 0.3 67 0.3 10 0.3 10 0.3 10 0.3 20 0.3 12 34 56 78 91011 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 1n2 2n2 3nc 4nc 5nc 6nc 7nc 8nc 9nc 10 nc 11 nc 12 nc 13 nc 14 gnd 15 v d 16 v in 17 gnd 18 nc 19 nc 20 nc 21 nc 22 p 23 s 24 r 25 n 26 n terminal code
mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 20~+100 40~+125 1500 (note 2) 60hz, sinusoidal, ac 1 minute, connection pins to heat-sink plate t c t stg v iso v v 20 0~v d +0.5 applied between : v d -gnd applied between : v in -gnd control supply voltage control input voltage v d v in condition symbol parameter ratings unit control (protection) part symbol ratings unit module case operation temperature storage temperature isolation voltage c c v rms total system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-pfc is 150 c (@ t c 100 c) however, to en- sure safe operation of the dip-pfc, the average junction temperature should be limited to t j(ave) 125 c (@ t c 100 c). parameter condition note 2 : t c measurement point v i v i(surge) v o v o(surge) v ces v rrm i i i i(125%) i 2 t tj maximum ratings (tj = 25 c, unless otherwise noted) main circuit part v rms v v v v v a rms a rms a 2 s c 264 500 450 500 600 600 15 18.7 75 20~+125 applied between : s-r applied between : s-r, surge value, non-operating applied between : p-n applied between : p-n, surge value, non-operating t c +90 c, v i = 200v, v o = 300v, f pwm = 20khz t c +90 c, v i = 200v, v o = 300v, f pwm = 20khz, 1 min non-repetitive value for 1msec of surge current (note 1) supply voltage supply voltage (surge) output voltage output voltage (surge) collector-emitter voltage repetitive peak reverse voltage input current (100% load) input current (125% load) i 2 t for fu sing junction temperature conditions symbol parameter ratings unit control terminals power terminals tc heat sink boundary heat sink tc
mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 2.6 2.2 1 10 1 10 2.05 2.50 0.067 ma ma a v t j = 25 c t j = 125 c v ce(sat) v f t on t rr t c(on) t off t c(off) i ces i r condition symbol parameter limits inverter igbt part inverter fwdi part case to fin, (per 1 module) thermal grease applied r th(j-c)q r th(j-c)f r th(c-f) min. c/w thermal resistance typ. max. unit i f = 30a condition symbol parameter limits min. typ. max. unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage forward voltage junction to case thermal resistance contact thermal resistance v d = 15v, v in = 5v, i c = 30a switching times v cc = 300v, v d = 15v i c = 20a, t j = 125 c, v in = 5v ? 0v inductive load collector-emitter cut-off current reverse current fwdi reverse recovery current v ce = 600v 2.0 1.6 0.23 0.14 0.14 0.43 0.23 13 v s s s s s c/w c/w control input current on threshold voltage off threshold voltage 16.5 3.0 3.0 0.45 3.7 12.5 13.0 15.0 0.8 0.7 0.3 3.0 2.0 trip level reset level v d i in v th(on) v th(off) uv dt uv dr v ma v v v v limits control (protection) part 13.5 1.3 10.3 10.8 v d = 15v, v in = 5v v d = 15v, v in = 0v applied between : v d -gnd control supply voltage condition symbol parameter min. typ. max. unit applied between : v d -gnd circuit current i d supply circuit under-voltage protection t j 125 c applied between : v in -gnd ma v r = 600v t j = 25 c t j = 125 c v d = 15v, v in = 5v i rr v cc = 300v, v d = 15v, i c = 20a, t j = 25 c
mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 vrms v v/ s khz v v supply voltage control supply voltage control supply variation pwm input frequency input on threshold voltage input off threshold voltage applied between : s-r applied between : v d -gnd t c 100 c, t j 125 c applied between : v in -gnd 264 16.5 1 v i v d ? v d f pwm v in(on) v in(off) condition symbol parameter limits min. typ. max. 90 13.5 1 unit recommended operation conditions 15.0 20 4.0~v d 0~1.0 note 3: measurement point of heat-sink flatness mounting screw : m4 ( note 3 ) condition parameter limits mounting torque weight heat-sink flatness min. mechanical characteristics and ratings typ. max. 0.98 50 unit 1.18 54 1.47 100 n m g m symbol + + measurement point heat sink place to contact a heat sink heat sink 3mm
mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 fig. 2 the dip-pfc internal circuit dip-pfc v d v in gnd r out s out v no v cc lvic p r s n2 n v in gnd
mitsubishi semiconductor PS51277-A transfer-mold type insulated type mar. 2003 dip-pfc wiring guidelines because dip-pfc switches large current at a very high speed, considerable large surge voltage is generated easily between p and n termi- nals. please pay attention to the following items: the area of p-co-n shown in fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. in addition, please add a bypass condenser co with good frequency response such as a polypropylene film condenser closely to the p and n terminals. the two igbt emitters are connected to the vno terminal of lvic inside the dip-pfc. if the internal wiring inductance shown as l1 and l2 in fig. 4 is too large, large surge voltage will be generated by di/dt. especially, the lower the temperature, the faster the s witching speed, therefore the larger the di/dt. this surge voltage applies to the vno and n terminals, which is possible to destruct lvic. in order to suppress the surge voltage, the external wiring method shown in fig. 4 is recommended. to reduce the parasitic wiri ng induc- tance, the wiring of the external terminals of n (n-1) and n (n-2) should be made as short as possible. please mount a fast clamp diode (eg01y@sanken) between n and control gnd terminals to prevent control gnd potential variation f rom the minus voltage of n terminal. r n / f lvic vno p dip pfc s v in n2 n (n-1, n-2) control ic mcu v d gnd co' co + p s + + r n-1 l1 l2 gnd vd control input gnd v d v in n2 n2 n-2 insert a diode here to restrain the ipm surge voltage, mount the condenser closely to the terminals to reduce the parasitic inductance, this wire should close to n terminal fig. 3 dip-pfc interface fig. 4 recommended wiring method
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